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Alif Semiconductor /AE722F80F55D5LS_CM55_HE_View /AON /SYSTOP_CLK_DIV

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Interpret as SYSTOP_CLK_DIV

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)PCLK_DIVISOR 0 (Val_0x0)HCLK_DIVISOR

PCLK_DIVISOR=Val_0x0, HCLK_DIVISOR=Val_0x0

Description

System Bus Clock Divider Control Register

Fields

PCLK_DIVISOR

SYST_PCLK clock divisor

0 (Val_0x0): Divide by 1

1 (Val_0x1): Divide by 2

2 (Val_0x2): Divide by 4

3 (Val_0x3): Divide by 4
HCLK_DIVISOR

SYST_HCLK clock divisor

0 (Val_0x0): Divide by 1

1 (Val_0x1): Divide by 2

2 (Val_0x2): Divide by 4

3 (Val_0x3): Divide by 4

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data